This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-150256, filed May 22, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to the write operation of a nonvolatile semiconductor memory and, more particularly, to a nonvolatile semiconductor memory represented by a NAND flash memory, which has a cell unit formed from a memory cell and select gate transistor.
FIG. 1 is a block diagram showing main part of a conventional NAND flash memory.
A memory cell array 11 has a plurality of cell units laid out in an array. Each cell unit is formed from a NAND array including a plurality of memory cells connected in series and two select gate transistors respectively connected to the two terminals of the NAND array, as is known.
On the memory cell array 11, word lines WL run in the row direction, and bit lines BL run in the column direction. The word lines WL are connected to a row decoder 12. The bit lines BL are connected to a sense amplifier 15 having a latch function for temporarily storing write data or read data. The sense amplifier is connected to an I/O buffer 14 through a column gate (column selecting switch) 13.
The column gate 13 is controlled by the output signal from a column decoder 16. A boost circuit 19 generates voltages necessary for write, erase, and read modes. For example, in the write mode, the boost circuit 19 generates a program potential Vpgm and applies it to the row decoder 12.
A row address signal is input to the row decoder 12. A column address signal is input to the column decoder 16. A control circuit 21 controls the operation of the row decoder 12, column gate 13, and column decoder 16 in accordance with the operation mode. For example, in the write mode, the control circuit 21 controls the switching timing of a potential to be applied to the word line WL (control gate line) or select gate line.
FIG. 2 is a block diagram showing the circuit arrangement of the memory cell array 11 shown in FIG. 1.
In this example, a cell unit is formed from a NAND array including four memory cells connected in series and two select gate transistors respectively connected to the two terminals of the NAND array.
The drain-side terminal of each cell unit is connected to a bit line BLj (j=0, 1, . . . ). Each bit line BLj is connected to a sense amplifier S/A having a latch function through a high voltage type MOS transistor. A control signal BLTR is input to the gate of the high voltage type MOS transistor. The source-side terminal of each cell unit is connected to a source line common to all cell units.
The group of memory cells connected to one word line (control gate line) WLi (i=0, 1, 2, 3) is normally called a page. One page is a unit of memory cells that are simultaneously write- or read-accessed in, e.g., a data write mode or data read mode for reading data from the memory cells to the sense amplifiers. To read data from the chip to the outside, the data of one page in the sense amplifiers are serially read from the chip to the outside in units of bits or in units of a plurality of bits.
The group of memory cells connected to a plurality of (four, in this example) word lines WL0, WL1, WL2, and WL3 between two select gate lines is normally called a block. One block is a unit of memory cells for which the erase is simultaneously executed in, e.g., a data erase mode. An erase mode executed for each block is called a block erase mode, and an erase mode executed for all blocks is called a chip erase mode.
The basic operations of the NAND flash memory, i.e., erase, write and read operations will be described next briefly.
Table 1 shows the potential relationship in the erase mode. Table 2 shows the potential relationships in the write and read modes.
In the erase mode, the well is set to an erase potential Vera (e.g., about 20V). All word lines in a selected block (block for which the erase is to be executed) are set to 0V, and all word lines in an unselected block (block for which no erase is to be executed) are set in a floating state.
A drain-side select gate line SGD and source-side select gate line SGS are also set in the floating state.
In the write mode, a selected bit line (bit line to which a memory cell to be write-accessed is connected) is set to 0V. An unselected bit line (bit line to which a write inhibit cell is connected) is set to, e.g., a power supply potential VDD. A selected word line (control gate line) is set to the program potential Vpgm (e.g., about 16V), and an unselected word line is set to an intermediate potential Vpass (e.g., about 8V).
In the selected block, the drain-side select gate line SGD is set to the power supply potential VDD, and the source-side select gate line SGS is set to 0V. In the unselected block, both the drain-side select gate line SGD and source-side select gate line SGS are set to 0V.
The program potential Vpgm may be stepped up by a predetermined amount dV in accordance with the number of times of write.
In the read mode, the bit line is precharged to, e.g., the clamp level of the bit line. After that, a selected word line (control gate line) is set to 0V, and an unselected word line is set to a read potential Vread (e.g., about 3.5V).
For a binary (2-level type) memory, since the threshold value of a xe2x80x9c1xe2x80x9d-cell is negative (less than 0V), and that of a xe2x80x9c0xe2x80x9d-cell is positive (more than 0V and less than Vread), all memory cells connected to an unselected word line are turned on. Hence, the potential of the bit line is determined by ON/OFF-controlling the memory cells connected to the selected word line. The change in bit line potential is detected by the sense amplifier having the latch function.
In the selected block, both the drain-side select gate line SGD and source-side select gate line SGS are set to the read potential Vread. In the unselected block, both the drain-side select gate line SGD and source-side select gate line SGS are set to 0V.
Details of the write operation of the NAND flash memory shown in FIGS. 1 and 2 will be described next.
Assumptions are that the word line WL2 shown in FIG. 2 is selected, of the memory cells connected to the word line WL2, a memory cell A indicated by a broken line is the selected cell (cell to be subjected to xe2x80x9c0xe2x80x9d-programming), and the remaining memory cells are unselected cells (cells to be subjected to xe2x80x9c1xe2x80x9dprogramming, i.e., write inhibit cell).
FIG. 3 is a waveform chart showing signal waveforms of a first conventional write scheme, i.e., self boost write scheme.
First, write data of one page are input from the outside of the chip to the sense amplifiers S/A (data load). Since xe2x80x9c0xe2x80x9d-programming (write operation for increasing the threshold value) is to be executed only for the memory cell A, data xe2x80x9c0xe2x80x9d is input to the sense amplifier S/A connected to a selected bit line BL2, and data xe2x80x9c1xe2x80x9d is input to the sense amplifiers S/A connected to remaining bit lines BL0, BL1, BL3, and BL4.
In the NAND flash memory, each sense amplifier S/A has a latch function (latch circuit) for temporarily storing write data. The sense amplifier S/A connected to the selected bit line BL2 latches the data xe2x80x9c0xe2x80x9d, and the sense amplifiers S/A connected to the bit lines BL0, BL1, BL3, and BL4 latch the data xe2x80x9c1xe2x80x9d.
Referring to the signal waveform chart of FIG. 3, BLxe2x80x9c0xe2x80x9d represents the bit line BL2 connected to the memory cell A to be subjected to xe2x80x9c0xe2x80x9d-programming, and BLxe2x80x9c1xe2x80x9d represents the bit lines BL0, BL1, BL3, and BL4 connected to cells (write inhibit cells) to be subjected to xe2x80x9c1xe2x80x9d-programming.
In the write operation, first, the control signal BLTR changes to xe2x80x9cHxe2x80x9d level (potential capable of sufficiently transferring the power supply potential VDD) to transfer the data in the sense amplifiers S/A to the bit lines BLj (j=0, 1, . . . ). That is, the bit line BL2 connected to the sense amplifier S/A with the data xe2x80x9c0xe2x80x9d changes to xe2x80x9c0xe2x80x9d (xe2x80x9cLxe2x80x9d level=0V), and the bit lines BL0, BL1, BL3, and BL4 connected to the sense amplifiers S/A with xe2x80x9c1xe2x80x9d the data xe2x80x9c1xe2x80x9d change to xe2x80x9c1xe2x80x9d (xe2x80x9cHxe2x80x9d level=VDD).
When the drain-side select gate line SGD in the selected block is set to the power supply potential VDD, the drain-side select gate transistors in the selected block are turned on. As a result, the data (potential) of the bit lines are transferred to the memory cells in the cell units in the selected block.
For example, since the selected bit line BL2 is at xe2x80x9c0xe2x80x9d, xe2x80x9c0xe2x80x9d (0V) is transferred to the memory cells in the cell unit connected to the selected bit line BL2. Since the unselected bit lines BL0, BL1, BL3, and BL4 are at xe2x80x9c1xe2x80x9d, xe2x80x9c1xe2x80x9d (VDDxe2x88x92Vth) is transferred to the memory cells in the cell units connected to the unselected bit lines BL0, BL1, BL3, and BL4.
Vth is the threshold value of the drain-side select gate transistor.
If all memory cells in the cell units in the selected block are in the erase state (xe2x80x9c1xe2x80x9d state), these memory cells are in the normally on state, so the channels of all memory cells in the cell unit connected to the selected bit line BL2 are charged to xe2x80x9c0xe2x80x9d (0V). The channels of all memory cells in the cell units connected to the unselected bit lines BL0, BL1, BL3, and BL4 are charged to xe2x80x9c1xe2x80x9d (VDDxe2x88x92Vth).
If the memory cells in the cell units in the selected block include a memory cell in the xe2x80x9c0xe2x80x9d-programming state (xe2x80x9c0xe2x80x9d state), that memory cell is turned off because the potentials of all word lines are currently 0V. For this reason, the channels of memory cells on the drain side of that memory cell are charged to 0V (in case of xe2x80x9c0xe2x80x9d-programming) or VDDxe2x88x92Vth (in case of xe2x80x9c1xe2x80x9dprogramming).
After that, in the selected block, the program potential Vpgm is applied to the selected word line WL2, and the intermediate potential Vpass (0 less than Vpass less than Vpgm) is applied to the unselected word lines WL0, WL1, and WL3.
Since the channels of the memory cells in the cell unit connected to the selected bit line BL2 are at xe2x80x9c0xe2x80x9d (0V), an electric field sufficient for the write (increase in threshold value by tunnelling) is applied across the channel and control gate electrode of the selected memory cell A.
On the other hand, when the program potential Vpgm and intermediate potential Vpass are applied to the word lines, the channel potential of the memory cells in the cell units connected to the unselected bit lines BL0, BL1, BL3, and BL4 rises due to capacitive coupling. Hence, no sufficient electric field is applied across the channel and the control gate electrode.
The channel potential of the memory cells in the cell units connected to the unselected bit lines BL0, BL1, BL3, and BL4 rises to the write inhibit potential that is mainly determined by the intermediate potential Vpass and a coupling ratio xcex1 of the memory cells.
With this operation, in the memory cells of one page connected to the selected word line WL2, xe2x80x9c0xe2x80x9d-programming (write operation for increasing the threshold value) is executed for the selected memory cell A, and xe2x80x9c1xe2x80x9d-programming (write operation for maintaining the xe2x80x9c1xe2x80x9d state) is executed for the remaining unselected memory cells.
In the above-described self boost write scheme, however, in transferring the potential VDD (xe2x80x9c1xe2x80x9d) of write inhibit level from the unselected bit lines BL0, BL1, BL3, and BL4 to the cell units in the selected block, so-called threshold voltage drop (drop of the transferring potential) occurs in the drain-side select gate transistors. That is, the potential VDDxe2x88x92Vth that is lower than the power supply potential VDD by the threshold value Vth of the select gate transistor is applied to the channels of the memory cells.
The potential VDDxe2x88x92Vth becomes the initial potential in raising the channel potential. That the initial potential decreases by Vth means that the final channel potential after channel boost also decreases by Vth. That is, since the channel potential of the write inhibit cell insufficiently rises, an erratic program (xe2x80x9c0xe2x80x9d-programming) readily occurs.
Write schemes developed aiming at preventing such an erratic program and improving reliability of a flash memory are known.
One of them is a write scheme called a select gate transistor boost scheme and is disclosed in, e.g., Jpn. Pat. Appln. KOKAI Publication Nos. 10-223866 and 11-185488. Another scheme is a write scheme called a source program scheme and is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 10-275481.
FIG. 4 is a waveform chart showing signal waveforms of a second conventional write scheme, i.e., select gate transistor boost scheme.
As a characteristic feature of this write scheme, to prevent the threshold voltage drop in transferring the power supply potential VDD (xe2x80x9c1xe2x80x9d) of write inhibit level to a cell unit, the gate potential of the drain-side select gate transistor at the time of VDD transfer is set to a potential VSG higher than the power supply potential VDD.
When the gate potential of the drain-side select gate transistor is set to the potential VSG higher than the power supply potential VDD, the initial channel potential of a memory cell before channel boost becomes higher than at least VDDxe2x88x92Vth. In addition, when the potential VSG is set to be VDD+Vth or more, the power supply potential VDD can be directly transferred to the cell unit.
As described above, according to the select gate transistor boost scheme, since the initial channel potential before channel boost can be set to be sufficiently high, the channel potential of the write inhibit cell can be sufficiently raised at the time of channel boost. Hence, any erratic program (xe2x80x9c0xe2x80x9d-programming) can be suppressed, and a very reliable flash memory can be provided.
In the signal waveforms shown in FIG. 4, the potentials of all word lines in the selected block are set to Vread (potential for turning on both the xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d cells: e.g., about 3.5V) in advance so as to turn on all memory cells in the selected block to transmit the initial potential to the channels of these memory cells and set the channels of write inhibit cells to a sufficiently high potential after channel boost.
FIG. 5 is a waveform chart showing signal waveforms of a third conventional write scheme, i.e., source program scheme.
As a characteristic feature of this write scheme, in consideration of the fact that the source line has a capacitance smaller than that of the bit line and can be charged to a voltage higher than VDD, the initial potential before channel boost is transferred from the source-side select gate transistor, i.e., source line to a cell unit.
First, a source potential CELSRC and the potential of the source-side select gate line SGS are set to Vread (about 3.5V). The potential Vread is transferred from the source line to the cell units through the source-side select gate transistors. Consequently, the channels of memory cells in all cell units in the selected block are charged to Vreadxe2x88x92Vth where Vth is the threshold value of the source-side select gate transistor.
After that, in the word lines in the selected block, the program potential Vpgm is applied to the selected word line, and the intermediate potential Vpass is applied to the unselected word lines. As a result, the channels of memory cells in all cell units in the selected block rise to the write inhibit potential.
After this channel boost, write data is transferred from the drain-side select gate transistors, i.e., bit lines to the cell units. That is, the potential of the drain-side select gate line SGD is set to the power supply potential VDD.
When the write data is xe2x80x9c0xe2x80x9d, the potential (0V) of the bit lines is transferred to the cell units through the drain-side select gate transistors. In this case, the channel potential of the memory cells in the cell units drops from the write inhibit potential to 0V.
When the write data is xe2x80x9c1xe2x80x9d, the potential of the bit lines is the power supply potential VDD, and the drain-side select gate transistors are cut off. In this case, the channel potential of the memory cells in the cell units keeps the write inhibit potential.
Hence, when the write data is xe2x80x9c0xe2x80x9d, an electric field sufficient for the write is applied across the channel and control gate electrode of a memory cell, so xe2x80x9c0xe2x80x9d-programming is executed. When the write data is xe2x80x9c1xe2x80x9d, no electric field sufficient for the write is applied across the channel and control gate electrode of a memory cell, so xe2x80x9c1xe2x80x9d-programming is executed.
As described above, according to the source program scheme, the initial potential before channel boost is transferred from the source line to a cell unit. Since the initial channel potential before channel boost can be set to be sufficiently high, the channel potential of a write inhibit cell can be sufficiently raised at the time of channel boost. Hence, any erratic program (xe2x80x9c0xe2x80x9d-programming) can be suppressed, and a very reliable flash memory can be provided.
In the self boost write scheme shown in FIG. 3 and the select gate transistor boost scheme shown in FIG. 4, to transfer the write data (0V or VDD) to a cell unit, the drain-side select gate line SGD is set to the power supply potential VDD or potential VSG higher than VDD. In the source program scheme shown in FIG. 5, after the program potential Vpgm is applied to the selected word line, the drain-side select gate line SGD is set to a value more than 0V (e.g., VDD) to allow transferring 0V from the bit line to the cell unit.
However, in recent years, the memory cell size is becoming small, and the pitch of word lines and select gate lines is also considerably decreasing. When the pitch of word lines (including select gate lines) becomes small, for example, the channel length of the select gate transistor is shortened, resulting in an increase in leakage current in cutting off the transistor.
Simultaneously, the capacitive coupling between adjacent word lines (including select gate lines) increases. This may raise, e.g., the gate potential of the select gate transistor to change the select gate transistor from the cut-off state to the ON state in applying the program potential Vpgm.
In this state, the initial potential (write inhibit potential) of the channels of precharged memory cells in the cell unit is removed to the bit line in applying the program potential Vpgm. As a consequence, no sufficient write inhibit potential can be obtained after channel boost. For this reason, an erratic program (xe2x80x9c0xe2x80x9d-programming) readily occurs, and the reliability of the flash memory degrades.
It is an object of the present invention to apply the initial potential to a cell unit, then apply the program potential Vpgm and intermediate potential Vpass to a word line, and apply to the gate electrodes of the select gate transistors a potential capable of sufficiently keeping the drain- and source-side select gate transistors in the cut-off state until channel boost is ended, thereby preventing the write inhibit potential from dropping due to a leakage current at the time of channel boost.
According to the present invention, there is provided a nonvolatile semiconductor memory comprising at least one memory cell, and a select gate transistor connected between a bit line and the at least one memory cell, wherein write operation is performed during continuous first, second, and third periods, and when gate potentials of the select gate transistor during these periods are represented by first, second, and third potentials, respectively, a relationship given by first potential greater than third potential greater than second potential holds.
Additional objects and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.